{"id":25655367,"date":"2026-07-28T18:16:47","date_gmt":"2026-07-28T12:46:47","guid":{"rendered":"https:\/\/entri.app\/blog\/?p=25655367"},"modified":"2026-07-28T18:17:41","modified_gmt":"2026-07-28T12:47:41","slug":"rtl-design-vs-verification-vs-physical-design","status":"publish","type":"post","link":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/","title":{"rendered":"RTL Design vs Verification vs Physical Design: Which Role Fits You?"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<label for=\"ez-toc-cssicon-toggle-item-6a68bacdd75e4\" class=\"ez-toc-cssicon-toggle-label\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/label><input type=\"checkbox\"  id=\"ez-toc-cssicon-toggle-item-6a68bacdd75e4\"  aria-label=\"Toggle\" \/><nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#Key_Takeaways\" >Key Takeaways<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#The_Three_Roles\" >The Three Roles<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#What_is_RTL_Design\" >What is RTL Design?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#What_is_Verification_DV\" >What is Verification (DV)?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#What_is_Physical_Design_Backend\" >What is Physical Design (Backend)?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#Side-by-Side_Comparison_India_2026\" >Side-by-Side Comparison (India, 2026)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#How_Indian_GCCs_Structure_these_Roles\" >How Indian GCCs Structure these Roles<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#Career_Growth_What_Comes_Next_in_Each_Track\" >Career Growth: What Comes Next in Each Track<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#Which_Role_Fits_You\" >Which Role Fits You<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#Conclusion\" >Conclusion<\/a><\/li><\/ul><\/nav><\/div>\n<p>Choose <strong>RTL design<\/strong> if you enjoy writing synthesizable digital logic in SystemVerilog or VHDL and turning a spec into working hardware. If you&#8217;d rather hunt bugs, build UVM testbenches, and prove logic does what it&#8217;s supposed to, choose <strong>verification<\/strong>.<\/p>\n<p>Choose <strong>physical design<\/strong> if floorplanning, timing closure, and converting a netlist into manufacturable layout sounds like your kind of puzzle.<\/p>\n<p>None of these roles work in isolation. RTL engineers write the code, verification engineers break it on purpose to catch every flaw before tape-out, and physical design engineers turn the surviving, verified logic into real silicon. In India&#8217;s fast-growing semiconductor ecosystem, all three tracks are hiring. But this is not equally, and not at the same pay.<\/p>\n<p style=\"text-align: center;\"><strong><a href=\"https:\/\/entri.app\/course\/embedded-systems-course-in-kerala\/?utm_source=embedded-systems&amp;utm_medium=blog_referral&amp;utm_campaign=online-vs-offline-embedded-systems-courses\" target=\"_blank\" rel=\"noopener\">Kickstart Your Embedded Systems Career and Turn Your Tech Passion into High-Demand Skills!<\/a><\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"Key_Takeaways\"><\/span><strong>Key Takeaways<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><strong>RTL:<\/strong> write synthesizable SystemVerilog\/VHDL. Optimize timing, area, power.<\/li>\n<li><strong>DV: <\/strong>build UVM, coverage, assertions. Catches bugs. Largest SoC effort.<\/li>\n<li><strong>Physical: <\/strong>floorplan, P&amp;R, CTS, timing signoff to GDSII.<\/li>\n<li><strong>Mar 2026:<\/strong> 3,549 GCC semiconductor roles. VLSI design and verification lead demand.<\/li>\n<li><strong>Freshers:<\/strong> \u20b94 LPA to \u20b912 LPA. Product MNCs pay more.<\/li>\n<li><strong>Bengaluru:<\/strong> VLSI hub. Hyderabad is a growing centre.<\/li>\n<li>No inherently better track. Pick them and specialise.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"The_Three_Roles\"><\/span><strong>The Three Roles<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<table>\n<tbody>\n<tr>\n<td><strong>Role<\/strong><\/td>\n<td><strong>What You Actually Do<\/strong><\/td>\n<\/tr>\n<tr>\n<td><strong>RTL Design<\/strong><\/td>\n<td>Write synthesizable SystemVerilog\/VHDL to implement digital blocks and hand off to synthesis and backend teams<\/td>\n<\/tr>\n<tr>\n<td><strong>Verification (DV)<\/strong><\/td>\n<td>Build UVM testbenches, assertions, and coverage plans to prove RTL matches the spec before tape-out<\/td>\n<\/tr>\n<tr>\n<td><strong>Physical Design<\/strong><\/td>\n<td>Floorplan, place-and-route, run clock-tree synthesis and static timing analysis (STA) to produce signoff-ready layout<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><span class=\"ez-toc-section\" id=\"What_is_RTL_Design\"><\/span><strong>What is RTL Design?<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-25655370 \" src=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134.webp\" alt=\"VLSI\" width=\"552\" height=\"309\" srcset=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134.webp 1500w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-300x168.webp 300w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-1024x574.webp 1024w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-768x431.webp 768w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-150x84.webp 150w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-750x421.webp 750w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/9134-1140x639.webp 1140w\" sizes=\"auto, (max-width: 552px) 100vw, 552px\" \/><\/p>\n<p>RTL (Register Transfer Level) design is where a written specification becomes actual digital hardware logic. Engineers translate architectural intent into synthesizable code on how data moves between registers each clock cycle. All this while balancing timing, area, and power.<\/p>\n<h4><strong>Core responsibilities:<\/strong><\/h4>\n<ul>\n<li>Convert micro-architecture specs into synthesizable RTL<\/li>\n<li>Optimize for timing, area, and power without breaking functional correctness<\/li>\n<li>Support synthesis and ECO (engineering change order) cycles alongside verification<\/li>\n<\/ul>\n<h4><strong>Skills you&#8217;ll need:<\/strong><\/h4>\n<ul>\n<li>SystemVerilog or VHDL<\/li>\n<li>Finite state machines and pipelining<\/li>\n<li>Clock-domain-crossing (CDC) awareness<\/li>\n<li>Basic Python\/shell scripting<\/li>\n<li>Comfort reading synthesis reports<\/li>\n<\/ul>\n<h4><strong>A typical day:<\/strong><\/h4>\n<p>Spec review \u2192 RTL coding \u2192 Unit-level simulation \u2192 Lint checks \u2192 Synthesis runs \u2192 ECOs, with frequent back-and-forth with verification engineers.<\/p>\n<h4><strong>Who it suits:<\/strong><\/h4>\n<p>People who like building deterministic systems and enjoy trading off speed, size, and power. If digital logic design and micro-architecture appealed to you more than debugging, this is likely your lane.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_is_Verification_DV\"><\/span><strong>What is Verification (DV)?<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Verification exists as a relevant way to answer one question with total confidence: Does this RTL do what the spec says, in every scenario?<\/p>\n<p>DV engineers do not write the feature. They try to break it, using constrained-random testing, functional coverage, assertions (SVA), and formal verification tools.<\/p>\n<h4><strong>Core responsibilities:<\/strong><\/h4>\n<ul>\n<li>Build verification plans and reusable UVM environments<\/li>\n<li>Drive functional coverage to closure and manage regressions<\/li>\n<li>Triage failures and work with RTL engineers to close bugs<\/li>\n<\/ul>\n<h4><strong>Skills you&#8217;ll need:<\/strong><\/h4>\n<ul>\n<li>Deep SystemVerilog and UVM methodology<\/li>\n<li>Assertion-based verification<\/li>\n<li>Coverage metric design<\/li>\n<li>Automation scripting<\/li>\n<li>A methodical, detail-obsessed mindset<\/li>\n<\/ul>\n<div class=\"lead-gen-block\"><a href=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2025\/05\/Concise-Embedded-System-Software-Engineering-Syllabus-2.pdf\" data-url=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2025\/05\/Concise-Embedded-System-Software-Engineering-Syllabus-2.pdf\" class=\"lead-pdf-download\" data-id=\"25612494\">\n<p style=\"text-align: center;\"><button class=\"btn btn-default\">Embedded System syllabus PDF<\/button><\/p>\n<\/a><\/div>\n<h4><strong>A typical day:<\/strong><\/h4>\n<p>Writing or extending testbenches \u2192 running regressions \u2192 analysing failure logs \u2192 chasing coverage holes.<\/p>\n<p>Verification is widely understood to consume the largest share of overall SoC development effort industry-wide. This is exactly why demand for skilled DV engineers stays consistently high.<\/p>\n<h4><strong>Who it suits:<\/strong><\/h4>\n<p>Engineers who enjoy finding edge cases nobody else noticed. Professionals who are into building test infrastructure more than the feature itself. It rewards patience and systematic thinking over raw creativity.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"What_is_Physical_Design_Backend\"><\/span><strong>What is Physical Design (Backend)?<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-25655372 \" src=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867.webp\" alt=\"VLSI\" width=\"364\" height=\"256\" srcset=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867.webp 2560w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-300x211.webp 300w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-1024x720.webp 1024w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-768x540.webp 768w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-1536x1080.webp 1536w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-2048x1440.webp 2048w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-150x105.webp 150w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-750x527.webp 750w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/19643219_web_hosting_5_-scaled-e1785242560867-1140x802.webp 1140w\" sizes=\"auto, (max-width: 364px) 100vw, 364px\" \/><\/p>\n<p>Physical design is where verified RTL becomes silicon. Once a netlist is functionally proven, backend engineers floorplan it.<\/p>\n<p>Not just that, they route the connections, build the clock tree, close timing, and run design-rules. They also run layout-versus-schematic (DRC\/LVS) checks for tape-out.<\/p>\n<h4><strong>Core responsibilities:<\/strong><\/h4>\n<ul>\n<li>Convert netlist to manufacturable layout meeting timing\/power\/area.<\/li>\n<li>Run STA and fix setup\/hold violations with ECOs.<\/li>\n<li>Coordinate DRC\/LVS and produce final GDSII.<\/li>\n<\/ul>\n<h4><strong>Skills you&#8217;ll need:<\/strong><\/h4>\n<ul>\n<li>Solid STA fundamentals<\/li>\n<li>Understanding of parasitics<\/li>\n<li>Familiarity with process design kits (PDKs) and node characteristics (FinFET, and increasingly GAA)<\/li>\n<li>TCL\/Python scripting<\/li>\n<li>Constraint-optimisation instincts<\/li>\n<\/ul>\n<h4><strong>A typical day:<\/strong><\/h4>\n<p>Floorplanning \u2192 Placement and Routing \u2192 Parasitic extraction \u2192 STA \u2192 ECO fixes \u2192 Signoff reviews.\u00a0This is an iterative, tool-heavy process that rewards patience.<\/p>\n<h4><strong>Who it suits:<\/strong><\/h4>\n<p>Engineers who enjoy spatial reasoning, constraint-based optimisation, and watching a design get physically tighter with every iteration.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Side-by-Side_Comparison_India_2026\"><\/span><strong>Side-by-Side Comparison (India, 2026)<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<table>\n<tbody>\n<tr>\n<td><strong>Aspect<\/strong><\/td>\n<td><strong>RTL Design<\/strong><\/td>\n<td><strong>Verification<\/strong><\/td>\n<td><strong>Physical Design<\/strong><\/td>\n<\/tr>\n<tr>\n<td>Core focus<\/td>\n<td>Implement logic in synthesizable RTL<\/td>\n<td>Prove correctness via UVM, coverage, formal<\/td>\n<td>Map RTL to silicon \u2014 floorplan, P&amp;R, STA, signoff<\/td>\n<\/tr>\n<tr>\n<td>Key skills<\/td>\n<td>SystemVerilog\/VHDL, synthesis, digital design<\/td>\n<td>SystemVerilog, UVM, SVA, coverage, scripting<\/td>\n<td>STA, parasitics, PDK knowledge, TCL\/Python<\/td>\n<\/tr>\n<tr>\n<td>Common tools<\/td>\n<td>Synopsys DC, Cadence Genus, Vivado<\/td>\n<td>VCS, Xcelium, Questa, JasperGold (formal)<\/td>\n<td>Cadence Innovus, Synopsys ICC2, Calibre, OpenROAD<\/td>\n<\/tr>\n<tr>\n<td>Fresher salary (approx.)<\/td>\n<td>\u20b94\u201312 LPA<\/td>\n<td>\u20b95\u201312 LPA<\/td>\n<td>\u20b95\u201311 LPA<\/td>\n<\/tr>\n<tr>\n<td>Mid-level (3\u20135 yrs)<\/td>\n<td>\u20b912\u201324 LPA<\/td>\n<td>\u20b912\u201325 LPA<\/td>\n<td>\u20b911\u201322 LPA<\/td>\n<\/tr>\n<tr>\n<td>Senior (6\u201310 yrs)<\/td>\n<td>\u20b922\u201345 LPA<\/td>\n<td>\u20b922\u201345 LPA<\/td>\n<td>\u20b922\u201342 LPA<\/td>\n<\/tr>\n<tr>\n<td>Remote-friendliness<\/td>\n<td>Moderate<\/td>\n<td>Higher<\/td>\n<td>Lower (often needs licensed EDA tools + local compute)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Salary ranges are indicative, compiled from multiple 2026 industry salary guides, and vary by company tier, node experience, and city.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"How_Indian_GCCs_Structure_these_Roles\"><\/span><strong>How Indian GCCs Structure these Roles<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Large SoC-focused GCCs generally run RTL, verification, and physical design as distinct teams with formal handoffs. RTL passes test interfaces to verification, then a signed-off netlist to backend.\u00a0Smaller design houses and FPGA teams often expect engineers comfortable across RTL and basic verification.<\/p>\n<p>India&#8217;s semiconductor GCC hiring has been accelerating through 2026, crossing 3,549 open roles by March, with small and mid-sized centres now driving momentum alongside legacy players.\u00a0Bengaluru and Hyderabad host the bulk of these centres. VLSI roles alone account for well over a third of all technical openings.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Career_Growth_What_Comes_Next_in_Each_Track\"><\/span><strong>Career Growth: What Comes Next in Each Track<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-25655371 \" src=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588.webp\" alt=\"VLSI\" width=\"461\" height=\"302\" srcset=\"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588.webp 2556w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-300x196.webp 300w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-1024x670.webp 1024w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-768x503.webp 768w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-1536x1005.webp 1536w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-2048x1340.webp 2048w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-150x98.webp 150w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-750x491.webp 750w, https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/28158098_framesawoperator_online_4-scaled-e1785242494588-1140x746.webp 1140w\" sizes=\"auto, (max-width: 461px) 100vw, 461px\" \/><\/p>\n<p>Every track has a credible senior path:<\/p>\n<ol>\n<li>RTL engineers move toward micro-architecture or design-lead roles<\/li>\n<li>Verification engineers progress into verification architect or DV manager positions<\/li>\n<li>Physical design engineers move into backend architect or CAD\/methodology roles<\/li>\n<\/ol>\n<h4><strong>For engineering students:<\/strong><\/h4>\n<p>Build one solid project per role. This can be a small FPGA-based RTL project, a UVM environment for an open-source core, or an OpenROAD\/OpenLane place-and-route exercise. A working project with a clear README beats a long resume line.<\/p>\n<h4><strong>For mid-career professionals pivoting from embedded or ECE roles:<\/strong><\/h4>\n<p>Target the one skill gap that matters most. This includes UVM for DV, STA for physical design, or advanced SystemVerilog for RTL. They can be backed by a measurable outcome (coverage achieved, timing fixed, area reduced).<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Which_Role_Fits_You\"><\/span><strong>Which Role Fits You<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Ask yourself:<\/p>\n<ol>\n<li><strong>Build something new, or break something that exists?<\/strong> Building points to RTL; breaking points to verification.<\/li>\n<li><strong>Long regression debugging, or visual, spatial problem-solving?<\/strong> The former suits verification; the latter suits physical design.<\/li>\n<li><strong>Comfortable depending on licensed EDA tools and heavier local infrastructure?<\/strong> Physical design leans on this more, affecting how remote-friendly your day-to-day can be.<\/li>\n<\/ol>\n<p>There&#8217;s no wrong answer. All the three tracks are in demand, and many engineers build working knowledge of more than one as they grow senior.<\/p>\n<p style=\"text-align: center;\"><strong><a href=\"https:\/\/entri.app\/course\/embedded-systems-course-in-kerala\/?utm_source=embedded-systems&amp;utm_medium=blog_referral&amp;utm_campaign=online-vs-offline-embedded-systems-courses\" target=\"_blank\" rel=\"noopener\">Kickstart Your Embedded Systems Career and Turn Your Tech Passion into High-Demand Skills!<\/a><\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"Conclusion\"><\/span><strong>Conclusion<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>RTL design, verification, and physical design aren&#8217;t competing career choices. They are three different ways of engaging with the same chip, each demanding a different kind of thinking.<\/p>\n<p>RTL rewards engineers who like building and optimising. Verification, on the other hand, rewards systematic bug-hunters. Physical design works well with spatial and constraint-driven problem-solvers.<\/p>\n<p>India&#8217;s semiconductor GCC hiring is surging and the demand spreads fairly evenly across all the three tracks. In this scenario, the smartest move is picking the one that matches how you naturally think and prefer things to be. Eventually build one strong project to prove it.<\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"2\">\n<p style=\"text-align: center;\"><b>RELATED POSTS<\/b><\/p>\n<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\"><a href=\"https:\/\/entri.app\/blog\/embedded-systems-vs-vlsi\/\" target=\"_blank\" rel=\"noopener\"><b>Embedded Systems vs VLSI: Which Has Better Career Scope?<\/b><\/a><\/td>\n<td>\n<p style=\"text-align: center;\"><a href=\"https:\/\/entri.app\/blog\/vlsi-embedded-systems-software-engineering\/\" target=\"_blank\" rel=\"noopener\"><b>VLSI vs Embedded Systems vs Software Engineering: Which Career Should You Choose?<\/b><\/a><\/p>\n<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\"><b> <a href=\"https:\/\/entri.app\/blog\/vlsi-skills-roadmap-for-freshers\/\" target=\"_blank\" rel=\"noopener\">VLSI Skills Roadmap for Freshers<\/a>\u00a0<\/b><\/td>\n<td>\n<p style=\"text-align: center;\"><b><\/b><b> <a href=\"https:\/\/entri.app\/blog\/embedded-systems-vs-vlsi\/\" target=\"_blank\" rel=\"noopener\">Embedded Systems vs VLSI: Which Has Better Career Scope?<\/a><\/b><\/p>\n<\/td>\n<\/tr>\n<tr>\n<td>\n<p style=\"text-align: center;\"><a href=\"https:\/\/entri.app\/blog\/embedded-systems-vs-robotics\/\" target=\"_blank\" rel=\"noopener\"><b>Embedded Systems vs Robotics: Which Career Path Is Better for You?<\/b><\/a><b>\u00a0<\/b><\/p>\n<\/td>\n<td style=\"text-align: center;\"><a href=\"https:\/\/entri.app\/blog\/engineering-manufacturing-gcc-roles\/\" target=\"_blank\" rel=\"noopener\"><b>Engineering &amp; Manufacturing GCC Roles: ER&amp;D, Automotive, and Semiconductor Careers in 2026<\/b><\/a><b> <\/b><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<div class=\"modal\" id=\"modal25612494\"><div class=\"modal-content\"><span class=\"close-button\">&times;<\/span>\n\n<div class=\"wpcf7 no-js\" id=\"wpcf7-f25612494-o1\" lang=\"en-US\" dir=\"ltr\" data-wpcf7-id=\"25612494\">\n<div class=\"screen-reader-response\"><p role=\"status\" aria-live=\"polite\" aria-atomic=\"true\"><\/p> <ul><\/ul><\/div>\n<form action=\"\/blog\/wp-json\/wp\/v2\/posts\/25655367#wpcf7-f25612494-o1\" method=\"post\" class=\"wpcf7-form init\" aria-label=\"Contact form\" novalidate=\"novalidate\" data-status=\"init\">\n<fieldset class=\"hidden-fields-container\"><input type=\"hidden\" name=\"_wpcf7\" value=\"25612494\" \/><input type=\"hidden\" name=\"_wpcf7_version\" value=\"6.1.6\" \/><input type=\"hidden\" name=\"_wpcf7_locale\" value=\"en_US\" \/><input type=\"hidden\" name=\"_wpcf7_unit_tag\" value=\"wpcf7-f25612494-o1\" \/><input type=\"hidden\" name=\"_wpcf7_container_post\" value=\"0\" \/><input type=\"hidden\" name=\"_wpcf7_posted_data_hash\" value=\"\" \/><input type=\"hidden\" name=\"_wpcf7cf_hidden_group_fields\" value=\"[]\" \/><input type=\"hidden\" name=\"_wpcf7cf_hidden_groups\" value=\"[]\" \/><input type=\"hidden\" name=\"_wpcf7cf_visible_groups\" value=\"[]\" \/><input type=\"hidden\" name=\"_wpcf7cf_repeaters\" value=\"[]\" \/><input type=\"hidden\" name=\"_wpcf7cf_steps\" value=\"{}\" \/><input type=\"hidden\" name=\"_wpcf7cf_options\" value=\"{&quot;form_id&quot;:25612494,&quot;conditions&quot;:[{&quot;then_field&quot;:&quot;-1&quot;,&quot;and_rules&quot;:[{&quot;if_field&quot;:&quot;course&quot;,&quot;operator&quot;:&quot;equals&quot;,&quot;if_value&quot;:&quot;Coding&quot;}]},{&quot;then_field&quot;:&quot;-1&quot;,&quot;and_rules&quot;:[{&quot;if_field&quot;:&quot;course&quot;,&quot;operator&quot;:&quot;equals&quot;,&quot;if_value&quot;:&quot;Commerce&quot;}]}],&quot;settings&quot;:{&quot;animation&quot;:&quot;yes&quot;,&quot;animation_intime&quot;:200,&quot;animation_outtime&quot;:200,&quot;conditions_ui&quot;:&quot;normal&quot;,&quot;notice_dismissed&quot;:false,&quot;repeater_remove_button&quot;:&quot;bottom&quot;,&quot;notice_dismissed_update-cf7-5.9.8&quot;:true,&quot;notice_dismissed_update-cf7-6.1.1&quot;:true}}\" \/>\n<\/fieldset>\n<p><span class=\"wpcf7-form-control-wrap\" data-name=\"full_name\"><input size=\"40\" maxlength=\"400\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"Name\" value=\"\" type=\"text\" name=\"full_name\" \/><\/span><br \/>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"phone\"><input size=\"40\" maxlength=\"400\" class=\"wpcf7-form-control wpcf7-tel wpcf7-validates-as-required wpcf7-text wpcf7-validates-as-tel\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"Phone\" value=\"\" type=\"tel\" name=\"phone\" \/><\/span><br \/>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"email_id\"><input size=\"40\" maxlength=\"400\" class=\"wpcf7-form-control wpcf7-email wpcf7-text wpcf7-validates-as-email\" aria-invalid=\"false\" placeholder=\"Email\" value=\"\" type=\"email\" name=\"email_id\" \/><\/span><br \/>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"language\"><select class=\"wpcf7-form-control wpcf7-select wpcf7-validates-as-required\" aria-required=\"true\" aria-invalid=\"false\" name=\"language\"><option value=\"\">Language<\/option><option value=\"Malayalam\">Malayalam<\/option><option value=\"Tamil\">Tamil<\/option><option value=\"Telugu\">Telugu<\/option><option value=\"Kannada\">Kannada<\/option><option value=\"Hindi\">Hindi<\/option><\/select><\/span><br \/>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"course\"><select class=\"wpcf7-form-control wpcf7-select wpcf7-validates-as-required course-field-select\" aria-required=\"true\" aria-invalid=\"false\" name=\"course\"><option value=\"\">Upskill in<\/option><option value=\"Embedded System Software Engineering\">Embedded System Software Engineering<\/option><option value=\"Robotics &amp; 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margin-bottom: -15px;\"> <div id=\"cf-turnstile-cf7-631552675\" class=\"cf-turnstile\" data-sitekey=\"0x4AAAAAABVigxtkiZeGTu5L\" data-theme=\"light\" data-language=\"auto\" data-size=\"normal\" data-retry=\"auto\" data-retry-interval=\"1000\" data-refresh-expired=\"auto\" data-refresh-timeout=\"auto\" data-action=\"contact-form-7\" data-callback=\"turnstileCF7Callback\" data-appearance=\"always\"><\/div> <br class=\"cf-turnstile-br cf-turnstile-br-cf7-631552675\"> <style>#cf-turnstile-cf7-631552675 { margin-left: -15px; }<\/style> <script>document.addEventListener(\"DOMContentLoaded\",function(){document.querySelectorAll('.wpcf7-form').forEach(function(e){e.addEventListener('submit',function(){if(document.getElementById('cf-turnstile-cf7-631552675')){setTimeout(function(){turnstile.reset('#cf-turnstile-cf7-631552675');},1000)}})})});<\/script> <\/div><br\/><input class=\"wpcf7-form-control wpcf7-submit has-spinner\" type=\"submit\" value=\"Submit\" \/>\n<\/p><div class=\"wpcf7-response-output\" aria-hidden=\"true\"><\/div>\n<\/form>\n<\/div>\n\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Choose RTL design if you enjoy writing synthesizable digital logic in SystemVerilog or VHDL and turning a spec into working hardware. If you&#8217;d rather hunt bugs, build UVM testbenches, and prove logic does what it&#8217;s supposed to, choose verification. Choose physical design if floorplanning, timing closure, and converting a netlist into manufacturable layout sounds like [&hellip;]<\/p>\n","protected":false},"author":132,"featured_media":25655368,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[802,2142],"tags":[],"class_list":["post-25655367","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-articles","category-embedded-systems"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.1 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>RTL Design vs Verification vs Physical Design: Which Role Fits You?<\/title>\n<meta name=\"description\" content=\"RTL design, verification, or physical design - which VLSI career fits you? Compare skills, salaries, and 2026 hiring trends to pick your path.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RTL Design vs Verification vs Physical Design: Which Role Fits You?\" \/>\n<meta property=\"og:description\" content=\"RTL design, verification, or physical design - which VLSI career fits you? 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Compare skills, salaries, and 2026 hiring trends to pick your path.\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/rtl-design-vs-verification-vs-physical-design\\\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/entri.app\\\/blog\\\/rtl-design-vs-verification-vs-physical-design\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/rtl-design-vs-verification-vs-physical-design\\\/#primaryimage\",\"url\":\"https:\\\/\\\/entri.app\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/07\\\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp\",\"contentUrl\":\"https:\\\/\\\/entri.app\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/07\\\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp\",\"width\":750,\"height\":375,\"caption\":\"RTL Design\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/rtl-design-vs-verification-vs-physical-design\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/entri.app\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Entri Skilling\",\"item\":\"https:\\\/\\\/entri.app\\\/blog\\\/category\\\/entri-skilling\\\/\"},{\"@type\":\"ListItem\",\"position\":3,\"name\":\"Embedded Systems\",\"item\":\"https:\\\/\\\/entri.app\\\/blog\\\/category\\\/entri-skilling\\\/embedded-systems\\\/\"},{\"@type\":\"ListItem\",\"position\":4,\"name\":\"RTL Design vs Verification vs Physical Design: Which Role Fits You?\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/entri.app\\\/blog\\\/\",\"name\":\"Entri Blog\",\"description\":\"\",\"publisher\":{\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/entri.app\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#organization\",\"name\":\"Entri App\",\"url\":\"https:\\\/\\\/entri.app\\\/blog\\\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/entri.app\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/10\\\/Entri-Logo-1.png\",\"contentUrl\":\"https:\\\/\\\/entri.app\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/10\\\/Entri-Logo-1.png\",\"width\":989,\"height\":446,\"caption\":\"Entri App\"},\"image\":{\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#\\\/schema\\\/logo\\\/image\\\/\"},\"sameAs\":[\"https:\\\/\\\/www.facebook.com\\\/entri.me\\\/\",\"https:\\\/\\\/x.com\\\/entri_app\"]},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/entri.app\\\/blog\\\/#\\\/schema\\\/person\\\/7b8f9d7bc43f2c2a314de3659894fc94\",\"name\":\"Surabhi Raveendran\",\"description\":\"Surabhi Raveendran is a content writer and English Literature postgraduate with a teaching background. She writes everything from blog posts to research pieces. She currently handles topics around Technical Skilling, Teacher Skilling and Digital Marketing.\",\"sameAs\":[\"https:\\\/\\\/www.linkedin.com\\\/in\\\/surabhi-raveendran\\\/\"],\"url\":\"https:\\\/\\\/entri.app\\\/blog\\\/author\\\/surabhi\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"RTL Design vs Verification vs Physical Design: Which Role Fits You?","description":"RTL design, verification, or physical design - which VLSI career fits you? Compare skills, salaries, and 2026 hiring trends to pick your path.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/","og_locale":"en_US","og_type":"article","og_title":"RTL Design vs Verification vs Physical Design: Which Role Fits You?","og_description":"RTL design, verification, or physical design - which VLSI career fits you? Compare skills, salaries, and 2026 hiring trends to pick your path.","og_url":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/","og_site_name":"Entri Blog","article_publisher":"https:\/\/www.facebook.com\/entri.me\/","article_published_time":"2026-07-28T12:46:47+00:00","article_modified_time":"2026-07-28T12:47:41+00:00","og_image":[{"width":750,"height":375,"url":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp","type":"image\/webp"}],"author":"Surabhi Raveendran","twitter_card":"summary_large_image","twitter_creator":"@entri_app","twitter_site":"@entri_app","twitter_misc":{"Written by":"Surabhi Raveendran","Est. reading time":"7 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#article","isPartOf":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/"},"author":{"name":"Surabhi Raveendran","@id":"https:\/\/entri.app\/blog\/#\/schema\/person\/7b8f9d7bc43f2c2a314de3659894fc94"},"headline":"RTL Design vs Verification vs Physical Design: Which Role Fits You?","datePublished":"2026-07-28T12:46:47+00:00","dateModified":"2026-07-28T12:47:41+00:00","mainEntityOfPage":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/"},"wordCount":1365,"publisher":{"@id":"https:\/\/entri.app\/blog\/#organization"},"image":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#primaryimage"},"thumbnailUrl":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp","articleSection":["Articles","Embedded Systems"],"inLanguage":"en-US"},{"@type":"WebPage","@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/","url":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/","name":"RTL Design vs Verification vs Physical Design: Which Role Fits You?","isPartOf":{"@id":"https:\/\/entri.app\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#primaryimage"},"image":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#primaryimage"},"thumbnailUrl":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp","datePublished":"2026-07-28T12:46:47+00:00","dateModified":"2026-07-28T12:47:41+00:00","description":"RTL design, verification, or physical design - which VLSI career fits you? Compare skills, salaries, and 2026 hiring trends to pick your path.","breadcrumb":{"@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#primaryimage","url":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp","contentUrl":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2026\/07\/RTL-Design_Verification_Physucal-Design_Embedded_66.webp","width":750,"height":375,"caption":"RTL Design"},{"@type":"BreadcrumbList","@id":"https:\/\/entri.app\/blog\/rtl-design-vs-verification-vs-physical-design\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/entri.app\/blog\/"},{"@type":"ListItem","position":2,"name":"Entri Skilling","item":"https:\/\/entri.app\/blog\/category\/entri-skilling\/"},{"@type":"ListItem","position":3,"name":"Embedded Systems","item":"https:\/\/entri.app\/blog\/category\/entri-skilling\/embedded-systems\/"},{"@type":"ListItem","position":4,"name":"RTL Design vs Verification vs Physical Design: Which Role Fits You?"}]},{"@type":"WebSite","@id":"https:\/\/entri.app\/blog\/#website","url":"https:\/\/entri.app\/blog\/","name":"Entri Blog","description":"","publisher":{"@id":"https:\/\/entri.app\/blog\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/entri.app\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/entri.app\/blog\/#organization","name":"Entri App","url":"https:\/\/entri.app\/blog\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/entri.app\/blog\/#\/schema\/logo\/image\/","url":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2019\/10\/Entri-Logo-1.png","contentUrl":"https:\/\/entri.app\/blog\/wp-content\/uploads\/2019\/10\/Entri-Logo-1.png","width":989,"height":446,"caption":"Entri App"},"image":{"@id":"https:\/\/entri.app\/blog\/#\/schema\/logo\/image\/"},"sameAs":["https:\/\/www.facebook.com\/entri.me\/","https:\/\/x.com\/entri_app"]},{"@type":"Person","@id":"https:\/\/entri.app\/blog\/#\/schema\/person\/7b8f9d7bc43f2c2a314de3659894fc94","name":"Surabhi Raveendran","description":"Surabhi Raveendran is a content writer and English Literature postgraduate with a teaching background. She writes everything from blog posts to research pieces. She currently handles topics around Technical Skilling, Teacher Skilling and Digital Marketing.","sameAs":["https:\/\/www.linkedin.com\/in\/surabhi-raveendran\/"],"url":"https:\/\/entri.app\/blog\/author\/surabhi\/"}]}},"_links":{"self":[{"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/posts\/25655367","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/users\/132"}],"replies":[{"embeddable":true,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/comments?post=25655367"}],"version-history":[{"count":2,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/posts\/25655367\/revisions"}],"predecessor-version":[{"id":25655377,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/posts\/25655367\/revisions\/25655377"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/media\/25655368"}],"wp:attachment":[{"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/media?parent=25655367"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/categories?post=25655367"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/entri.app\/blog\/wp-json\/wp\/v2\/tags?post=25655367"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}