Intel Hiring: Physical Design Layout Engineer (Bangalore)

Introduction

Intel is hiring a Physical Design Layout Engineer for its Bangalore location under the ICE (Intel Central Engineering) group. The role targets fresh graduates and early-career engineers with hands-on training or experience in physical design.

Job Overview

Intel’s Bangalore team is looking for a Physical Design Layout Engineer to create and optimize chip designs at the physical level, including cell and block-level semi-custom layouts, FUB-level floor plans, and schematic-to-layout verification.

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Key Responsibilities

• Develop and refine physical chip designs: cell and block-level semi-custom layouts, FUB-level floor plans, abstract view generation, and schematic-to-layout verification.
• Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.
• Utilize parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, and full-chip assembly techniques.
• Collaborate across teams to troubleshoot complex design challenges and deliver high-quality solutions.
• Participate in project methodologies, flow developments, and verification processes.

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Required Skills

• TCL
• Layout design
• Floor Planning
• ICC2
• Parasitic Extraction
• Full-Chip Assembly
• Schematic-to-Layout Verification
• Verification (reliability/debug)

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Education & Eligibility

How to Apply

Use the official Intel Workday link you shared:

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About the Role’s Impact

As a Physical Design Layout Engineer, you will work on critical elements of chip layouts—ensuring accuracy and functionality from cell/block level up to full-chip assembly. Your work supports Intel’s technology development and advanced chip design initiatives.