NVIDIA ASIC Verification Engineer Job Opening

Introduction

NVIDIA is hiring for the role of ASIC Verification Engineer in Hyderabad, India, and Bengaluru, India. The job is listed as a full-time engineering role and is associated with job ID JR2020484.

This opening is for candidates with a background in Computer Science or Electronics Engineering or equivalent experience, and the listing indicates 0–2 years of experience.

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Job Details

Roles & Responsibilities

• The work includes building tools, infrastructure, and test frameworks used in RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon.
• Understanding Tegra system architecture, with a focus on all IPs in the SOC that are involved in boot and security features.
• The tools that you build give Design and Verification teams the ability to access registers/memory/DMA engines and other features in their unit. The tools also enable test re-use across multiple platforms (RTL, models, Emulation, and Silicon). The gamut of tools is wide and you also develop features used for Silicon bring up (example: FUSE, ATE, Security, Flash/DMA, Board I2Cs, USB debug devices among others). We strive for the highest quality of test frameworks and tools that we deliver from this team.
• You would assess and build C-model or RTL-simulation capability that allows us to simulate the features before Silicon arrival in a pre-silicon environment.

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Eligibility Information

• BS or MS in Computer Science or Electronics Engineering or equivalent experience with 0-2 years of experience
• Strong programmer who is proficient with C, C++, Python.
• Understanding of SOC and System Architecture.
• Understanding of How the SOC Devices like DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU function.
• Operating System and Device-Driver concepts and ability to write no-OS test frameworks – i.e tests that run directly on the bare-metal SOC.
• A good programmer takes pride in building scalable and maintainable software.
• Understanding Hardware and/or Software development life cycle.

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Preferred Qualification

• Previous experience handling Silicon Bringup and in enabling Emulation/FPGA related test frameworks.
• Exposure to Testbench architectures (C++ testbenches, SV/UVM based testbenches).
• Verilog and System Verilog coding skills are a plus.